As the trend towards miniaturization of semiconductor devices continues, variation in lithographic features becomes increasingly more significant. Variation in the lithographic process can lead to features being undersized. These undersized features are randomly distributed throughout a wafer, and cause higher resistance, and thus, also may cause poor performance in the chip. Furthermore, such defects adversely impact the overall yield of the semiconductor fabrication process. Therefore, it is desirable to have a method and system for identifying and repairing defects during the semiconductor fabrication process.